Vector processing in computer architecture

This article is about Processors (including In vector processor or array processor is a vectors. This is in contrast to Vector machines appeared in the early 1970s and dominated History [ ] Early research and development [ ] Vector processing development began in the early 1960s at the Solomon project. Solomon's goal was to dramatically increase math performance by using a large number of simple In 1962, Westinghouse cancelled the project, but the effort was restarted by the Computer for operations with functions [ ] A Supercomputers [ ] The first vector supercomputers are the The basic ASC (i.e., "one pipe") ALU used a pipeline architecture that supported both scalar and vector computations, with peak performance reaching approximately 20 MFLOPS, readily achieved when processing long vectors. Expanded ALU configurations supported "two pipes" or "four pipes" with a corresponding 2X or 4X performance gain. Memory bandwidth was sufficient to support these expanded modes. The STAR-100 was otherwise slower than CDC's own supercomputers like the The vector technique was first fully exploited in 1976 by the famous The Cray design used vector chaining. The Cray-1 normally had a performance of about 80 MFLOPS, but with up to three chains running it could peak at 240MFLOPS and averaged around 150 – far faster than any machine of the era. Other examples followed. Throughout, Cray continued to be the performance leader, continually beating the competition with a series of machines th...

Vector- or array-processing computers are essentially designed to maximize the concurrent activities inside a computer and to match the bandwidth of data flow to the execution speed of various subsystems within a computer. This chapter reviews architectural advances in vector-processing computers. It describes the two major classes of vector machines—namely, the pipeline computers and array processors. Problems associated with designing pipeline computers are also presented with examples from the Texas Instruments Advanced Scientific Computer (TI-ASC), Control Data STring ARay (STAR-100) and CYBER-205 Computers, Cray Research CRAY-1, and Floating-Point Systems AP-120B. The chapter describes the architectures of recently developed SIMD array processors. Further, it examines the development experiences of the Burroughs Scientific Processor (BSP) and the Goodyear Aerospace Massively Parallel Processor (MPP). Recent research works on array and pipeline processors are also summarized. The chapter concludes with the evaluation of the performance of pipeline and array processors and explores various optimization techniques for vector operations. Hardware, software, and algorithmic issues of vector-processing systems and future trends of vector computers are also discussed. • Previous chapter in volume • Next chapter in volume

Knights Landing architecture Jim Jeffers, ... Avinash Sodani, in Intel Xeon Phi Processor High Performance Programming (Second Edition), 2016 Vector processing unit The VPU is the vector and FP arithmetic execution unit of Knights Landing and is responsible of providing support for x87, MMX, SSE, AVX, and AVX-512 instructions, as well as integer divides. There are two VPUs connected to the core. These are tightly integrated into the pipeline, with AU dispatching instructions directly into the VPUs. The VPUs are mostly symmetrical, and each is able to provide a steady-state throughput of one AVX-512 instruction per cycle, providing a peak of 64 SP or 32 DP FP operations per cycle from the pair of VPUs available per core (i.e., 2 VPUs per core, 1 AVX-512 instruction per cycle per VPU, FMA offers 16 DP, or 32 SP operations per instruction using AVX-512 registers that are 8 DP or 16 SP wide, 2×1×16=32 DP or 2×1×32=64 SP). One of the VPUs is extended to provide support for the legacy FP instructions, such as x87, MMX, and a subset of byte and word SSE instructions. Each VPU contains a 20-entry FP operation RSs that issues out-of-order one μop per cycle. The FP RS are different from the IEU RS and MEU RS in that they, to help reduce their size, do not hold source data; the FP μops read their source data from FP RB and FP RF after they issue from the FP RS, spending an extra cycle between RS and execution compared to integer and memory μops. Most FP arithmetic operations have a l...

Instructor: Sudha Aravindan Sudha Aravindan has taught high school Math and professional development in Information Technology for over 10 years. Sudha has a Doctorate of Education degree in Mathematics Education from the University of Delaware, USA, a Masters degree in English Literature from the University of Kerala, India, a Bachelor of Education degree in Teaching of Math from the University of Kerala, India, and a Bachelor of Science degree in Math, Physics and Statistics from the University of Kerala, India. Sudha has a certificate in Java programming and Statistical Analysis. Sandra was writing a program for computing Geographical Information Systems (GIS) data for 20,000 rivers and lakes in the Midwest. The calculations require a large number of variables and data types including image data, map data, and data from satellite images. Sandra created 300 different variables to hold data for the various computations. When the program was executed, it had to be left overnight to complete. Her teammate Jen was running a similar program and it took only a fraction of the time. Jen said she was using a vector for processing the data. We can simply define vector processing as the process of using vectors to store a large number of variables for high-intensity data processing. The two main characteristics of a vector are that it helps with fast processing and that the size of the vector doesn't need to be decided in advance. A vector processor is a CPU in a computer with par...